1. Field of the Disclosure
The present disclosure generally relates to memory systems and, more particularly, to an analog delay locked loop (DLL) or phase locked loop (PLL) with delay stage interweaving.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves a microprocessor. Delay-locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving the microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident or has a fixed time delay relationship (or “locked”) with the rising edge of a second clock signal (e.g., the memory's internal clock).
FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 14 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 14 may constitute memory address pins or address bus 17, data pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17–19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 20. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 20 generally arranged in rows and columns to store data in rows and columns. Each memory cell 20 may store a bit of data. A row decode circuit 22 and a column decode circuit 24 may select the rows and columns in the memory cells 20 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 20 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) unit 26. The I/O unit 26 may include a number of data output buffers (not shown) to receive the data bits from the memory cells 20 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O unit 26 may further include a clock synchronization unit or delay locked loop (DLL) 28 to synchronize the external system clock (e.g., the clock used by the memory controller (not shown) to clock address, data and control signals between the memory chip 12 and the controller) with the internal clock used by the memory 12 to perform data write/read operations on the memory cells 20. In the embodiment of FIG. 1, the DLL 28 is an analog DLL, which is described in more detail below with reference to FIG. 2.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 14 on the chip 12. These pins, ash mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 depicts a simplified block diagram of the analog delay-locked loop (DLL) 28 shown in FIG. 1. The analog DLL 28 is a 4-phase DLL, generating the Ph0, Ph90, Ph180, and Ph270 signals at its output 33. On the other hand, a 2-phase analog DLL would generate, for example, a Ph0 and a Ph180 signals only. The DLL 28 receives a reference clock (ClkREF) 46 as an input and generates a set of output clock signals (Ph0, Ph90, Ph180, Ph270, Ph360) at the output 33 of a voltage controlled delay line (VCDL) 32. The Ph0 and Ph360 signals are, in turn, fed back into a phase detector 30 whose operation is discussed below. In the discussion herein, the notation “Ph0” is used to refer to a clock signal that is substantially in phase with the reference clock 46, whereas the “Ph360” signal is substantially 360° out of phase with ClkREF 46. Similarly, the Ph90 clock signal is substantially 90° out of phase with ClkREF 46, the Ph180 clock is substantially 180° out of phase with ClkREF 46, and Ph270 clock is substantially 270° out of phase with the reference clock 46. It is noted that the reference clock 46 is interchangeably referred to herein as “ClkREF”, “ClkREF signal”, “Ref clock signal”, “Ref clock” or “system clock”; whereas each of the various output clocks (Ph0, Ph90, Ph180, etc.) is individually referred to herein as a “phase signal” and collectively as “phase signals.” The reference clock 46 is typically the external system clock serving the microprocessor (or memory controller) (both not shown) or a delayed/buffered version of the external system clock.
One or more of the output phase signals Ph0, Ph90, etc., or signals derived from them, may be used as “internal clock(s)” by the SDRAM 12 to perform data read/write operations on memory cells 20 and to transfer the data out of the SDRAM to the data requesting device (e.g., a microprocessor (not shown)). As can be seen from FIG. 2, the phase signals are generated using delay lines (not shown) in the VCDL 32, which introduces a specific delay into the input Ref clock 46 to obtain the “lock” condition—i.e., to obtain specific output clocks or phase signals (Ph0, Ph90, etc.) having a predetermined phase relationship with the input reference clock 46. The phase detector (PD) 30 compares the relative timing of the Ph0 and Ph360 phase signals (both of which relate to the reference clock 46 in a determined manner) to generate one of a pair of direction signals—the UP signal 34 or the DN (down) signal 35—depending on the phase difference between the Ph0 and Ph360 signals. The direction signal outputs are fed to a charge pump 36, which generates a control voltage signal Vctrl 38 whose value at a given instant in time depends on the inputs received from the phase detector 30. Thus, the voltage level of the control voltage Vctrl 38 is representative of the phase difference between the Ph0 and Ph360 phase signals and, hence, between the ClkREF signal 46 and its 360° delayed version. The control voltage signal 38 is fed to a bias generator 40, which generates a pair of bias voltage outputs or bias signals—a PMOS (p-channel metal oxide semiconductor) bias voltage VBP 42 and an NMOS (n-channel MOS) bias voltage VBN 43—based on the voltage level of the input Vctrl signal 38. For example, in one embodiment, the PMOS bias voltage VBP may be substantially equal to or may vary directly with Vctrl, the control input to the bias generator. In that case, when the value of Vctrl goes high, the value of VBP goes high whereas the value of VBN goes low. And, when the value of Vctrl goes low, the value of VBP also goes low proportionately whereas the value of VBN goes high.
The bias voltages are applied to the VCDL unit 32 to control the delay imparted therein to the reference clock 46 input thereto. In one embodiment, when VBP goes high and VBN goes low, the delay imparted by VCDL 32 increases; whereas, when VBP goes low and VBN goes high, the delay decreases. Although a single output line 33 is illustrated in FIG. 2, the VCDL 32 may have separate output lines (not shown) to output each of the phase signals Ph0, Ph90, etc., individually. It is noted here that additional constructional details or circuit details (of individual circuit units, e.g., the charge pump 36 or the bias generator 40) for the analog DLL 28 in FIG. 2 is not provided herein for the sake of brevity and also because such details are known to one skilled in the art.
As noted before, the analog DLL 28 in FIG. 2 is a 4-phase DLL, which may be employed when the external or system clock 46 has a frequency (e.g., 800 MHz) that substantially differs from the frequency (e.g., 400 MHz) of the memory's internal clock (not shown). On the other hand, if the internal and external frequencies are almost equal (e.g., both equal to 800 MHz), then a 2-phase DLL (generating only Ph0 and Ph 180 outputs) may suffice as is known in the art.
It is observed that the frequency range of operation of the DLL 28 (i.e., the available range of delay) is dependent on the range of Vctrl 38, the gain of various circuit elements in the DLL 28, the number of various VCDL stages constituting the VCDL unit 32, and the PVT (process, voltage, temperature) variations during circuit fabrication and at run time. Generally, if too many VCDL stages (not shown) are used for low frequency operation, the analog DLL 28 requires a lot of current at high frequency because some of those delay stages in VCDL 32 may be unnecessarily kept turned ON during high frequency operation. At high reference clock frequencies, it may not be preferable to increase the number of VCDL stages because that may also increase the corresponding overall delay. However, on the other hand, if less than optimum number of VCDL stages are employed, the VCDL may not properly function at low input clock frequencies. For example, if delay at each VCDL stage (not shown) is in the range of 300–700 ps (picoseconds) (a range of delay is available because of the voltage-controlled nature of the VCDL operation), then four (4) VCDL stages may be needed to obtain a delay range of 1.2 ns–2.8 ns for a low frequency operation. However, with the same number (4) of VCDL stages, it may not be possible to obtain a delay range of 1 ns–4 ns which may be needed to accommodate a higher reference clock frequency (e.g., a frequency having a clock period tCK=1 ns). On the other hand, if the number of VCDL stages are reduced to three (3) to obtain the delay range of 0.9 ns–2.1 ns (so as to accommodate the minimum clock period tCK of 1 ns), then the reduced number of delay stages would fail to accommodate lower clock frequencies having periods in the range of 2.1 ns–2.8 ns.
It is noted here that the discussion presented hereinabove equally applies to an analog phase-locked loop (PLL) that may be used in place of the analog DLL 28 in the memory chip 12 as is known in the art. The PLL implementation may include a VCO (Voltage Controlled Oscillator) instead of the VCDL 32 for the DLL version. However, the VCDL and VCO may be generally considered as voltage-controlled frequency monitoring units. Because of substantial similarity in the construction and operation of an analog PLL and an analog DLL, only the DLL implementation is discussed herein. However, it is evident that the entire DLL-related discussion presented herein equally applies to a PLL-based embodiment, of course with suitable PLL-specific modifications as may be apparent to one skilled in the art.